Chagit L.

Responsibilities:

• Designed and implemented a complete UVM-based verification environment Built a full system-level UVM environment for the YAPP Router, integrating YAPP Input, three Channel UVCs, HBUS UVC, and Clock & Reset UVC using virtual interfaces, UVM configuration database, and TLM connectivity.

• Defined the verification plan (vPlan) and test objectives Authored the verification plan outlining features to verify, test scenarios, coverage goals, and alignment between tests, coverage, and design requirements.

• Developed an active YAPP agent and transaction flow Implemented an active YAPP agent including sequencer, driver, and monitor, with protocol-aware transaction modeling for packet generation, driving, and observation.

• Implemented a virtual / multichannel sequencer Designed a virtual sequencer to coordinate stimulus between YAPP traffic and HBUS register configuration, enabling synchronized system-level test execution.

• Built a reference model driven by HBUS register configuration Developed a reference model that mirrors router behavior based on HBUS register writes, validating packet legality (destination address, packet size, router enable state) before generating expected results.

• Developed a TLM-based scoreboard for end-to-end verification Created a scoreboard using TLM analysis ports and per-channel queues to compare expected versus actual packets across all output channels, detecting routing errors, drops, and mismatches.

• Authored system-level sequences and implemented functional coverage Developed directed and randomized sequences covering valid and invalid traffic scenarios, including illegal addresses, oversized packets, parity errors, and router enable/disable behavior. Implemented functional coverage for packet attributes, routing behavior, and cross scenarios to measure verification completeness.