Chaya Z.

Responsibilities:

• Integration of Multiple UVCs into a Unified Verification Environment Implemented full integration of the YAPP Input UVC, three Channel UVCs, the HBUS UVC, and the Clock & Reset UVC using UVM Configuration Database, Virtual Interfaces, and TLM connections to create a complete and synchronized verification environment.

• Development of a Multichannel Sequencer for Coordinated Test Execution Designed and implemented a multichannel sequencer to coordinate activity between the YAPP Sequencer and the HBUS Sequencer, enabling complex test scenarios and synchronized multi-interface operations.

• Implementation of a Router Reference Model Driven by HBUS Register Updates Developed a reference model that mirrors DUT behavior by tracking HBUS register writes, validating packet legality (address, size, enable state), and forwarding only valid packets for further scoreboard analysis.

• Construction of a TLM-Based Scoreboard for Multi-Channel Packet Verification Built a scoreboard using TLM analysis imports, per-channel queues, packet cloning, and custom comparison logic to validate end-to-end packet correctness across all router output channels.

• Creation of System-Level Test Sequences for Full Router Behavior Validation Authored advanced test sequences that combine YAPP and HBUS operations, including register configuration, enabling/disabling the router, sending packets to multiple addresses, and verifying error handling for illegal address, oversize packets, and parity faults.