Diti K.

Responsibilities:

• Developed a complete UVM-based verification environment for the YAPP Router, including transaction modeling, driver, sequencer, monitor, and agent, fully aligned with the packet protocol and router specification.

• Designed a comprehensive library of UVM sequences, from basic packet flows to full system-level tests, verifying routing behavior across all channels, varying packet sizes, illegal addresses, and parity error scenarios.

• Integrated the DUT using Virtual Interfaces and combined multiple UVCs—YAPP, HBUS, Channels, and Clock/Reset—into a unified, synchronized verification environment supporting full end-to-end system testing.

• Implemented a modular Scoreboard and Reference Model using UVM TLM analysis ports to compare expected vs. actual packet routing, detect drops and errors, and provide detailed end-of-test reporting.

• Developed functional coverage models capturing key routing scenarios, including combinations of address, packet length, parity conditions, and drop behavior, ensuring thorough and measurable verification completeness.

• Modeled the router’s control and status registers using UVM RAL, executed read/write operations via HBUS sequences, and validated register values against DUT behavior and Scoreboard results.