Yaffi Y.

Responsibilities:

• Designed and implemented a complete UVM verification environment for a multi-channel YAPP Router, including agents, monitors, drivers, sequencers, and configuration objects.

• Developed a full register model (RAL), including frontdoor/backdoor accesses, mirror & predict mechanisms, and integrated it into the testbench with a dedicated register sequencer and adapter.

• Implemented a multi-channel sequencer and coordinated parallel traffic generation across multiple router interfaces, including constrained-random and directed sequences.

• Built a functional scoreboard with a cycle-accurate reference model using TLM analysis FIFOs to check routing correctness, packet integrity, and protocol compliance.

• Created comprehensive functional coverage for packet structure, routing behavior, state transitions, error cases, and register operations; aligned coverage items with the vPlan.

• Wrote a detailed vPlan including assumptions, verification features, test scenarios, coverage goals, and expected DUT behaviors; maintained traceability between vPlan features and coverage.

• Research: Performance improvement with multithreaded packet generation and scoreboard parallelization.